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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16705-1E
32-bit Proprietary Microcontrollers
CMOS
FR60 MB91319R Series
MB91316/316A/F318R/F318S/FV319R
DESCRIPTION
The MB91319R series is the microcontrollers which use a high-performance 32-bit RISC-CPU and contains various types of I/O resources for the embedded control that requires high-performance and high-speed CPU processing. It is suitable for the embedded control in TV or PDP, requiring high-performance CPU processing power. This product is one of the FR60* family based on the FR30/40 family CPU with enhanced bus access. It is applicable to faster-speed application. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURE
* FR CPU * 32-bit RISC, load/store architecture with a five-stage pipeline * Operating frequency : 40 MHz (Use of PLL : Oscillation 10 MHz) * 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle * Embedded application optimized instructions : Memory-to-memory transfer, bit processing, barrel shift, and other instructions. * High-level language support instructions : Function entry/exit instructions, multiple register load/store instructions. * Register interlock functions: Facilitating coding in assemblers * Built-in multiplier with instruction-level support 32-bit multiplication with sign : 5 cycles 16-bit multiplication with sign : 3 cycles (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006 FUJITSU LIMITED All rights reserved
MB91319R Series
* * * * Interrupt (PC, PS save) : 6 cycles, 16 priority levels Harvard architecture allowing program access and data access to be executed simultaneously Instruction prefetch function implemented by a four-word queue in the CPU Instruction compatible with FR family
* Bus interface This bus interface is used for internal macro IF (USB, OSDC) * CS1, CS2, and CS3 areas are connected as following : CS1 area : Reserved, CS2 area : USB function, CS3 area : OSDC * Built-in memory Memory RAM Memory for program Memory for font
MB91FV319R 48 Kbytes Flash memory : 1 Mbyte Flash memory : 512 Kbytes
MB91F318R/F318S 48 Kbytes Flash memory : 1 Mbyte MASK ROM : 384 Kbytes
MB91316/316A 32 Kbytes MASK ROM : 512 Kbytes MASK ROM : 384 Kbytes
* DMAC (DMA Controller) * 5 channels (ch.0 and ch.1 are connected to USB function. ) * Two transfer sources (internal peripherals/software) * Specifying of addressing mode 32-bit full address (increased/decreased/fixed) * Transfer modes (demand transfer, burst transfer, step transfer, block transfer) * Selectable transfer data size : 8, 16, or 32-bits * Bit search module (for REALOS) * Search for the position of the bit "1"/"0"-changed first in one word from the MSB * Reload timer (including a channel for REALOS) * 16-bit timer: 3 channels * The internal clock is selectable from 2/8/32 divisions. * UART * Full-duplex double buffer * 5 channels * Selectable parity ON/OFF * Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable * Built-in timer for dedicated baud rate * External clock can be used as transfer clock. * Assorted error detection functions (for parity, frame, and overrun errors) (Continued)
2
MB91319R Series
* I2C Interface * * 4 channels (built-in bridge function) * Master/slave sending and receiving * Clock synchronization function * Detecting transmitting direction function * Bus error detection function * Standard mode (Max 100 kbps) /High speed mode (Max 400 kbps) supported * Built-in FIFO function with 16-byte data each for transmit/receive * Arbitration function * Slave address and general call address detection function * Start condition repeated generation and detection * 10-bit/7-bit slave address * Interrupt controller * Total of external interrupt pin is 5. (one non-maskable interrupt pin (NMI) and four normal interrupt pins (INT3 to INT0) ) * Interrupt from internal peripheral * Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt * At the STOP, available use for Wake Up * A/D converter * 10-bit resolution, 10 channels * Successive approximation type converter. Conversion time: Approx. 10 s * Conversion modes (one-shot conversion mode, scanning conversion mode) * Activation trigger (software / external trigger) * PPG * 4 channels are incorporated. * 16-bit down counter, 16-bit data register with buffer for setting cycles * The internal clock is selectable from 1/4/16/64 divisions. * PWC * 1 channel (1 input) is incorporated. * 16-bit up counter * Easy digital low pass filter * Multi function timer * 4 channels are incorporated. * Low pass filter eliminating noise below the clock setting * Capable of pulse width measurement according to fine settings using seven types of clock signals * Event count function from pin input * Interval timer function using seven kinds of clock and external input clock * USB function * Full speed * double buffer of USB2.0 version * CONTROL IN/OUT, BULK IN/OUT, INTERRUPT IN (Continued)
3
MB91319R Series
(Continued) * OSDC function * RGB: each 3 bits (16 colors available among 512 colors) * Analog RGB output: Max 50 MHz * Digital RGB output: Max 90 MHz * A font in 24 x 32 dots can be displayed up to 80 x 32. * Two-layered display of MAIN/CC (Font in CC layer is fixed at 18 dots in horizontal axis) * 4096 characters at the maximum (including 16 characters for font RAM) * Closed caption decoder function * 2 channels are incorporated. * CC decode function * ID-1 (480i/480p) decode function * PLL for video clock * 3 PLLs generating dot clock and VBI clock * Other interval timer * 16-bit timer : 3 channels * Watchdog timer * I/O port * Max 88 ports * Other features * Built-in oscillation circuit as clock source * INIT is prepared as a reset pin. * Watchdog timer reset and software reset are also available. * Stop mode and sleep mode are supported as low-power consumption mode. * Gear function * Built-in time-base timer * Package : LQFP-176, 0.5mm pitch, 24 mm x 24 mm * CMOS technology : 0.18 m * Power supply voltage : 3.3 V 0.3 V, 1.8 V 0.15 V 2-power supply * : "Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips."
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MB91319R Series
PIN ASSIGNMENT
(TOP VIEW)
VSYNC DCKI DCKO FH VOB1 VOB2 VDDI R2 R1 R0 G2 G1 G0 B2 B1 B0 UDP UDM VDDE X0B VSS X1B VDDI PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 P17 P16/ATRG P15/PPG3 P14/PPG2 P13/PPG1 P12/PPG0 P11/TMO3 P10/TMO2 P07/TMO1 P06/TMO0 P05/TO2 P04/TO1 P03/TO0 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 HSYNC1 HSYNC2 HSYNC3 VDDE VSS VGS1/VCI1 CPO1 VSSP1 VDDP1 VGS2/VCI2 CPO2 VSSP2 VDDP2 VGS3/VCI3 CPO3 VSSP3 VDDP3 VDDR VREF VR0 ROUT VSSR VDDG GOUT VSSG VDDB BOUT VSSB VIN0 VIN1 VDDIS VSSS VDDI AVCC AVRH AVSS/AVRL PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 P94/TMI1 P93/TMI0 P92/RIN P91/SCK1 P90/SO1 P87/SI1 P86/SCK0 P85/SO0 P84/SI0 P83/SDA1 P82/SCL1 P81/SDA0 P80/SCL0 INIT MD3 MD2 MD1 MD0 ICD3 ICD2 ICD1 ICD0 ICS2 ICS1 ICS0 IBREAK ICLK TRST VDDI X1 VSS X0 VDDE P32 P31 P30 P27 P26 P25 P24 P23 P22 P21/AN9 P20/AN8 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
P02/SCK4/TIN2 P01/SO4/TIN1 P00/SI4/TIN0 P74 P73 P72 P71 P70 VDDE VSS VDDI P57 P56 P55 P54 P53 P52/SCK3 P51/SO3 P50/SI3 P47/SCK2 P46/SO2 P45/SI2 P44/SDA4 P43/SDA3 P42/SCL4 P41/SCL3 P40/SDA2 P37/SCL2 P36/TRG3 P35/TRG2 P34/TRG1 P33/TRG0 NMI PA2/INT3 PA1/INT2 PA0/INT1 VDDI X1A VSS X0A VDDE P97/INT0 P96/TMI3 P95/TMI2
(FPT-176P-M07)
5
MB91319R Series
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name HSYNC1 HSYNC2 HSYNC3 VDDE VSS VGS1/VCI1 CPO1 VSSP1 VDDP1 VGS2/VCI2 CPO2 VSSP2 VDDP2 VGS3/VCI3 CPO3 VSSP3 VDDP3 VDDR VREF VR0 ROUT VSSR VDDG GOUT VSSG VDDB BOUT VSSB VIN0 VIN1 VDDIS VSSS VDDI AVCC AVRH I/O Circuit type* G G G K K K K K K K K K K Function Vertical synchronous input 1 Vertical synchronous input 2 Vertical synchronous input 3 I/O power supply Ground Guard band ground Charge pump output Dot clock PLL ground Dot clock PLL power supply Guard band ground Charge pump output Dot clock PLL ground Dot clock PLL power supply Guard band ground Charge pump output Dot clock PLL ground Dot clock PLL power supply D/A power supply for R Power supply reference input Resistor connection pin R output (analog) D/A ground for R D/A power supply for G G output (analog) D/A ground for G D/A power supply for B B output (analog) D/A ground for B Data slicer input 0 Data slicer input 1 Data slicer power supply Data slicer ground Internal logic power supply A/D power supply A/D reference power supply (Continued) 6
MB91319R Series
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin Name AVSS/AVRL PC0 AN0 PC1 AN1 PC2 AN2 PC3 AN3 PC4 AN4 PC5 AN5 PC6 AN6 PC7 AN7 P20 AN8 P21 AN9 P22 P23 P24 P25 P26 P27 P30 P31 P32 VDDE X0 VSS X1 VDDI
I/O Circuit type* E E E E E E E E E E C C C C C C C C C A A A/D ground General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port Analog input General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port 3.3 V power supply 10 MHz oscillation pin Ground 10 MHz oscillation pin
Function
Internal logic power supply (Continued) 7
MB91319R Series
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
Pin Name TRST ICLK IBREAK ICS0 ICS1 ICS2 ICD0 ICD1 ICD2 ICD3 MD0 MD1 MD2 MD3 INIT P80 SCL0 P81 SDA0 P82 SCL1 P83 SDA1 P84 SI0 P85 SO0
I/O Circuit type* B M L O O O P P P P F F F L B J J J J C C
Function DSU tool reset (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU clock (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU break (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU status (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) DSU data (In MB91F318R/F318S, this pin is the open pin so do not connect with other pins.) Mode pin Mode pin Mode pin Mode pin Initial (reset) pin General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port UART0 serial input General-purpose port UART0 serial output (Continued)
8
MB91319R Series
Pin No. 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
Pin Name P86 SCK0 P87 SI1 P90 SO1 P91 SCK1 P92 RIN P93 TMI0 P94 TMI1 P95 TMI2 P96 TMI3 P97 INT0 VDDE X0A VSS X1A VDDI PA0 INT1 PA1 INT2 PA2 INT3 NMI P33 TRG0
I/O Circuit type* C C C C C C C C C O A A O O O B C General-purpose port
Function UART0 clock input/output General-purpose port UART1 serial input General-purpose port UART1 serial output General-purpose port UART1 clock input/output General-purpose port PWC input General-purpose port Multi-functional timer 0 input General-purpose port Multi-functional timer 1 input General-purpose port Multi-functional timer 2 input General-purpose port Multi-functional timer 3 input General-purpose port External interrupt input 0 3.3 V power supply 32 kHz oscillation pin Ground 32 kHz oscillation pin Internal logic power supply General-purpose port External interrupt input 1 General-purpose port External interrupt input 2 General-purpose port External interrupt input 3 NMI input General-purpose port PPG0 trigger input (Continued)
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MB91319R Series
Pin No. 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
Pin Name P34 TRG1 P35 TRG2 P36 TRG3 P37 SCL2 P40 SDA2 P41 SCL3 P42 SCL4 P43 SDA3 P44 SDA4 P45 SI2 P46 SO2 P47 SCK2 P50 SI3 P51 SO3 P52 SCK3 P53 P54 P55 P56 P57
I/O Circuit type* C C C N N N N N N C C C C C C C C C C C General-purpose port PPG1 trigger input General-purpose port PPG2 trigger input General-purpose port PPG3 trigger input General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C clock pin General-purpose port I2C clock pin General-purpose port I2C data pin General-purpose port I2C data pin General-purpose port UART2 serial input General-purpose port UART2 serial output General-purpose port UART2 clock output General-purpose port UART3 serial input General-purpose port UART3 serial output General-purpose port UART3 clock output General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port
Function
(Continued) 10
MB91319R Series
Pin No. 122 123 124 125 126 127 128 129 130
Pin Name VDDI VSS VDDE P70 P71 P72 P73 P74 P00 SI4 TIN0 P01
I/O Circuit type* C C C C C C Ground 3.3 V power supply General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port UART4 serial input
Function Internal logic power supply
Reload timer 0 trigger input General-purpose port C UART4 serial output Reload timer 1 trigger input General-purpose port C UART4 clock input Reload timer 2 trigger input C C C C C C C C C General-purpose port Reload timer 0 output General-purpose port Reload timer 1 output General-purpose port Reload timer 2 output General-purpose port Multi-functional timer 0 output General-purpose port Multi-functional timer 1 output General-purpose port Multi-functional timer 2 output General-purpose port Multi-functional timer 3 output General-purpose port PPG0 output General-purpose port PPG1 output (Continued) 11
131
SO4 TIN1 P02
132
SCK4 TIN2 P03 TO0 P04 TO1 P05 TO2 P06 TMO0 P07 TMO1 P10 TMO2 P11 TMO3 P12 PPG0 P13 PPG1
133 134 135 136 137 138 139 140 141
MB91319R Series
(Continued) Pin No. 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Pin Name P14 PPG2 P15 PPG3 P16 ATRG P17 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VDDI X1B VSS X0B VDDE UDM UDP B0 B1 B2 G0 G1 G2 R0 R1 R2 VDDI VOB2 VOB1 FH DCKO DCKI VSYNC
I/O Circuit type* C C C C C C I C C C H C A A USB D D D D D D D D D D D D D G G General-purpose port PPG2 output General-purpose port PPG3 output General-purpose port
Function
A/D conversion trigger input General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port Internal power supply 48 MHz oscillation pin Ground 48 MHz oscillation pin 3.3 V power supply USB function USB function RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output Internal logic power supply Translucent color period output OSD display period output Horizontal synchronous output Dot clock output Dot clock input Vertical synchronous output
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE". 12
MB91319R Series
I/O CIRCUIT TYPE
Type
X1
Circuit type
Remarks * Oscillation circuit * Feedback resistance X0 : 1 M X0A : 10 M
Clock input
A
X0
Standby control * CMOS level hysteresis input * With pull-up resistor
P-ch
P-ch
N-ch
B
Digital input * CMOS level output * CMOS level hysteresis input * With standby control Digital output
N-ch
P-ch
C
Digital output
Digital input Standby control (Continued)
13
MB91319R Series
Type
Circuit type
2.5 V P-ch
Remarks * 2.5 V CMOS level output * CMOS level hysteresis input * With standby control Digital output
N-ch
D
Digital output
Digital input Standby control * * * * CMOS level output CMOS level hysteresis input With standby control With analog input switch
P-ch
Digital output
N-ch
Digital output
E Analog input Control Digital input Standby control * CMOS level input * Without standby control
P-ch
F
N-ch
Digital input (Continued)
14
MB91319R Series
Type
Circuit type
Remarks * CMOS level hysteresis input * Without standby control
P-ch
G
N-ch
Digital input * * * * CMOS level output CMOS level hysteresis input With standby control With pull-down resistor
Pull-down control
P-ch
Digital output
N-ch
H
N-ch
Digital output
Digital input Standby control * * * * CMOS level output CMOS level hysteresis input With standby control With pull-up resistor
P-ch
P-ch
Digital output
N-ch
I
Digital output
Digital input Standby control (Continued)
15
MB91319R Series
Type
Circuit type
Remarks * Open drain output * CMOS level hysteresis input * With standby control Open drain control
P-ch
N-ch
J
Digital output
Digital input Standby control Analog pin
P-ch
K
N-ch
Analog input or Analog output
* CMOS level hysteresis input * With pull-down resistor
P-ch
L
N-ch
N-ch
Digital input CMOS level output
P-ch
Digital output M
N-ch
Digital output
(Continued) 16
MB91319R Series
Type
Circuit type * * * *
Remarks 3 ports for I2C CMOS level hysteresis input CMOS level output With stop control
P-ch
Open drain control
N-ch
Digital output
N
P-ch
Digital input } Control Digital input Control Open drain control
Digital output
N-ch
Digital input
P-ch
Open drain control
N-ch
Digital output
P-ch
* CMOS level output * CMOS level hysteresis input * Without standby control Digital output
O
N-ch
Digital output
Digital input (Continued)
17
MB91319R Series
(Continued) Type Circuit type * * * * Remarks CMOS level output CMOS level hysteresis input Without standby control With pull-down resistor
P-ch
Digital output P
N-ch N-ch
Digital output
Digital input
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MB91319R Series
HANDLING DEVICES
* Preventing a Latch-up A latch-up can occur on a CMOS IC under following conditions. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. - When a voltage higher than VDDE or VDDI or a voltage lower than VSS is applied to an input or output pin. - When a voltage higher than the rating is applied between VDDE or VDDI and VSS. * Handling of Unused Input Pins Do not leave an unused input pin open since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * Power Supply Pins If more than one VDDE or VDDI or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch-up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VDDE or VDDI and VSS pin of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 F be connected between VDDE or VDDI and VSS pin at circuit points close to the device as a bypass capacitor. * Crystal Oscillation Circuit Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another as possible. It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be used to increase the expectation of stable operation. Please ask the Oscillation maker to evaluate the oscillational characteristics of the crystal and this device. * Mode Pins (MD0 to MD3) In order to prevent mistakes due to noise, and sending them into test mode, connect these pins as close to VDDE and VSS pins, and at as low an impedance as possible. * Tool Reset Pins (TRST) Be sure to input the same signal as the INIT when this pin is not used for the tool. The same processing is executed for the mass product. * Power-on Immediately after power-on, be sure to apply setting initialization reset (INIT) with INIT pin. Also immediately after power-on, keep the INIT pin at the "L" level until the oscillator has reached the required oscillation stabilization wait time. (For initialization by INIT from the INIT pin, the oscillation stabilization wait time is set to the minimum value.) * Source Oscillation Input at Power-on At power-on, be sure to input a source clock until the oscillation stabilization wait time is reached.
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MB91319R Series
* Precautions at Power-On/Power-Off * Precautions when turning on and off VDDI pin and VDDE pin To ensure the reliability of LSI devices, do not continuously apply only VDDE pin for about a minute when VDDI is off. When VDDE pin is changed from off to on, the power noise may make it impossible to retain the internal state of the circuit. Power-on : Supply voltage of VDDI pin analog Supply voltage of VDDE pin signal Power-off : Signal Supply voltage of VDDE pin analog Supply voltage of VDDI pin * Indeterminate Output when the Power is Turned On When turning on the power, the output pin may remain indeterminate until internal power supply becomes stable. * Clock About the attention when the external clock is used When the external clock is used, in principle, supply a clock signal to the X0 (X0A, X0B) pin and an oppositephase clock signal to the X1 (X1A, X1B) pin at the same time. However, in this case the stop mode (oscillator stop mode) must not be used (This is because, in STOP mode, the X1 (X1A, X1B) pin stops at "H" output) . At 12.5 MHz or less, the device can be used with the clock signal supplied only to the X0 (X0A, X0B) pin. * Using an External Clock (normal)
X0, X0A, X0B X1, X1A, X1B
MB91319R Series
Note: The STOP mode (oscillation stop mode) cannot be used.
* Using an External Clock (available at 12.5 MHz or less)
X0, X1A, X1A
OPEN
X1, X1A, X1B
MB91319R Series
Note : The X1 (X1A, X1B) pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 (X0A, X0B) pin.
20
MB91319R Series
* Restrictions Common in MB91319R series (1) Clock control block Take the oscillation stabilization wait time during Low level input to the INIT pin. (2) Bit Search Module The 0-detection data register (BSD0) , 1-detection data register (BSD1) , and transition-detection data register (BSDC) are only word-accessible. (3) I/O port Ports are accessed only in bytes. (4) Low-power Consumption Mode * Be sure to use the following sequence to enter standby mode if synchronous standby mode is being used (the SYNCS bit (bit 8) of the TBCR (timebase counter control register) is set) : (LD1 #value_of_stanby, R0) (LD1 #_STCR, R12) STB R0, @R12 ; Write to standby control register (STCR) LDUB @R12, R0 ; STCR read for synchronous standby LDUB @R12, R0 ; Dummy re-read of STCR NOP ; NOP x 5 for adjusted timing NOP NOP NOP NOP (5) Notes on the PS register The PS register is processed prior to the execution of some instructions, which may cause the exception handling described below to trigger breakpoints in interrupt processing routines or to update the displayed contents of the PS register when the debugger is being used. In all of these situations, because the microcontroller has been designed to correctly perform reprocessing after returning from an EIT, the operation before and after the EIT is performed according to the specifications. * The following operations are performed if, in the instruction immediately before a DIVOU or DIVOS instruction, a user interrupt or an NMI occurs, single-step execution is performed, or break is selected from the emulator menu. (1)The D0 and D1 flags are updated in advance. (2)An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3)Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1) . * If the any of the ORCCR, STILM, MOV Ri or PS instructions is executed in order to enable interrupts when a user interrupt source or NMI source is in the interrupt occurred state, the following operations are performed. (1)The PS register is updated in advance. (2)An EIT handling routine (user interrupt and NMI) is executed. (3)Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1) .
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MB91319R Series
(6) Watchdog timer The watchdog timer that is built into this product monitors the program to see if it performs a reset delay operation within a fixed period of time. And, that resets the CPU if the reset delay operation is not performed due to a runaway program. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution. A watchdog reset may not be generated in the above situation caused by the system running out of control. In that case, reset (INIT) by external INIT pin. (7) Notes on using A/D The MB91319R series has built-in A/D converter. Do not supply a voltage higher than VDDE to the AVCC. * Software reset in synchronous mode When software reset in the synchronous mode is used, the following two conditions must be satisfied before setting the SRST bit of the STCR (standby control register) to 0. - Set the interrupt enable flag (I-Flag) to the interrupt disabled (I-Flag = 0). - Do not use NMI. (8) Simultaneous generation of software break and user interrupt/NMI (only for MB91FV319R) If a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may cause the following phenomena. * The debugger stops pointing to a location other than the programmed breakpoints. * The halted program is not re-executed correctly. If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. (9) Step execution of RETI instruction In an environment where interrupts frequently occur during single-step execution, only the relevant interrupt processing routines are executed repeatedly during single-step execution of the RETI instruction. This will prevent the main routine and low-interrupt-level programs from being executed. To avoid it, do not singlestep RETI instructions. When the relevant interrupt routine no longer requires being debugged, disable the relevant interrupt and perform debugging. (10) About an operand break Do not apply a data event break to access to the area containing the address of a stack pointer. (11) Example of batch file for configuration To debug a program downloaded to internal RAM, be sure to execute the following batch file after executing RESET. #----------------------------------------------------------------------------------#Set MODR (0x7fd) = Enable In memory + 16-bit External Bus set mem/byte 0x7fd = 0x5 #---------------------------------------------------------------------------------(12) Address in the built-in Flash/ROM area (Flash memory for program : 1 Mbyte product) The address 0X0017FFF8 in the built-in Flash/ROM area has been reserved. You must configure the FE.
22
MB91319R Series
BLOCK DIAGRAM
FR60 CPU core
32 32 Bit search
Flash 1 Mbyte*1 MASK ROM 512 Kbytes*1
RAM EVA, Flash 48 Kbytes, MASK ROM 32 Kbytes
Bus Converter
DMAC 5 channels
32 to 16 Adapter
External I/F Font Flash
USB function
Clock control
Flash 512 Kbytes*2 MASK ROM 384 Kbytes*2
OSDC
Interrupt controller
UART 5 channels
I2C 4 channels
A/D converter 10 channels
CC Decoder 2 channels
External interrupt
Ports
PWC 1 channel
PPG 4 channels
Reload timer 3 channels
Multi-function 4 channels
*1 : MB91FV319R and MB91F318R/F318S contain the program ROM of 1 Mbyte flash memory, and MB91316/316A contain that of 512 Kbytes MASK ROM. *2 : MB91FV319R contains the font ROM of 512 Kbytes flash memory, and MB91F318R/F318S, MB91316/316A contain that of 384 Kbytes MASK ROM.
23
MB91319R Series
MEMORY SPACE
The FR family has 4 GB of logical address space (232 addresses) available to the CPU by linear access. * Direct Addressing Areas The following address space area is used for I/O. This area is called the direct addressing area. The addresses of operands in this area may be specified directly in an instruction. The direct addressing area varies depending on the size of the data being accessed as follows. Byte data access : 000H to 0FFH Half word data access : 000H to 1FFH Word data access : 000H to 3FFH * Memory Map Single-chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H 0002 F800H 0003 C000H 0004 0000H 0005 0000H 0006 0000H 0007 0000H OSDC 0008 0000H 0018 0000H 0020 0000H Flash ROM 1 1 Mbytes*2 Flash ROM 2 512 Kbytes*3
Access prohibited Font RAM Built-in RAM*1 Access prohibited Access prohibited USB function
Access prohibited
FFFF FFFFH
*1 : Built-in RAM area of MB91F318R/F318S, MB91FV319R is 0003 4000H to 0003 FFFFH (48 Kbytes) . Built-in RAM area of MB91316/316A is 0003 8000H to 0003 FFFFH (32 Kbytes) . *2 : MB91316/316A is 0008 0000H to 000F FFFFH (MASK ROM 512 Kbytes). *3 : MB91F318R/F318S and MB91316/316A are 0018 0000H to 001F FFFFH (MASK ROM 384 Kbytes) .
24
MB91319R Series
I/O MAP
This shows the correspondence between the memory space area and various peripheral resource registers. [How to read the table] Address 00000000H Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port Data Register
Read/Write attribute Initial value of register after a reset Register name (First-column register at address 4n; second-column register at address 4n + 2) Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial Value "1" "0" : Initial Value "0" "X" : Initial Value "X" " - " : No physical register at this location Register +0 PDR0[R/W] XXXXXXXX PDR4[R/W] XXXXXXXX PDR8[R/W] XXXXXXXX PDRC[R/W] XXXXXXXX ADCTH[R/W] XXXXXX00 +1 PDR1[R/W] XXXXXXXX PDR5[R/W] XXXXXXXX PDR9[R/W] XXXXXXXX ADCTL[R/W] 00000X00 +2 PDR2[R/W] XXXXXXXX PDRA[R/W] -----XXX +3 PDR3[R/W] XXXXXXXX PDR7[R/W] --XXXXXX PDRB[R/W] XXXXXXXX R-bus Port Data Register
Address 000000H to 00000FH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H
Block
Reserved
ADCH[R/W] 00000000 00000000 ADAT1[R] XXXXXX00 00000000 ADAT3[R] XXXXXX00 00000000 ADAT5[R] XXXXXX00 00000000 ADAT7[R] XXXXXX00 00000000 (Continued) 25 10-bit A/D Converter
ADAT0[R] XXXXXX00 00000000 ADAT2[R] XXXXXX00 00000000 ADAT4[R] XXXXXX00 00000000 ADAT6[R] XXXXXX00 00000000
MB91319R Series
Address 000034H to 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H
Register +0 EIRR [R/W] 00000000 DICR [R/W] -------0 +1 ENIR [R/W] 00000000 HRCL [R/W] 0--11111 +2 ELVR [R/W] 00000000 TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] ----0000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] ----0000 00000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] ----0000 00000000 SIDR0 [R/W] XXXXXXXX SCR0 [R/W] 00000100 DRCL0 [W] -------SCR1 [R/W] 00000100 DRCL1 [W] -------SCR2 [R/W] 00000100 DRCL2 [W] -------SCR3 [R/W] 00000100 DRCL3 [W] -------SCR4 [R/W] 00000100 DRCL4 [W] -------SMR0 [R/W] 00--0-0UTIMC0 [R/W] 0--00001 SMR1 [R/W] 00--0-0UTIMC1 [R/W] 0--00001 SMR2 [R/W] 00--0-0UTIMC2 [R/W] 0--00001 SMR3 [R/W] 00--0-0UTIMC3 [R/W] 0--00001 SMR4 [R/W] 00--0-0UTIMC4 [R/W] 0--00001 +3
Block
Reserved
Ext int DLYI/I-unit
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX TMRLR2 [W] XXXXXXXX XXXXXXXX SSR0 [R/W] 00001-00
Reload Timer 0
Reload Timer 1
Reload Timer 2
UART0 U-TIMER 0 UART1 U-TIMER 1 UART2 U-TIMER 2 UART3 U-TIMER 3 UART4 U-TIMER 4 (Continued)
UTIM0 [R] (UTIMR [W]) 00000000 00000000 SSR1 [R/W] 00001-00 SIDR1 [R/W] XXXXXXXX
UTIM1 [R] (UTIMR [W]) 00000000 00000000 SSR2 [R/W] 00001-00 SIDR2 [R/W] XXXXXXXX
UTIM2 [R] (UTIMR [W]) 00000000 00000000 SSR3 [R/W] 00001-00 SIDR3 [R/W] XXXXXXXX
UTIM3 [R] (UTIMR [W]) 00000000 00000000 SSR4 [R/W] 00001-00 SIDR4 [R/W] XXXXXXXX
UTIM4 [R] (UTIMR [W]) 00000000 00000000
26
MB91319R Series
Address 000088H to 00008CH 000090H 000094H 000098H 00009CH 0000A0H to 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH
Register +0 PWCCL[R/W] 0000--00 PWCCH[R/W] 00-00000 +1 +2 +3
Block
Reserved
PWCD[R] XXXXXXXX XXXXXXXX PWCC2[R/W] 000----Reserved
PWC PWC Reserved IFDR0 [R/W] 00000000
PWCUD[R] XXXXXXXX XXXXXXXX IFN0 [R] 00000000 IBCR0 [R/W] 00000000 IFRN0 [R/W] 00000000 IBSR0 [R/W] 00000000 IFCR0 [R/W] 00-00000
ITBA0 [R/W] ------00 00000000 ISMK0 [R/W] 01111111 ICCR0 [R/W] 0-011111 IFCR1 [R/W] 00-00000 ISBA0 [R/W] 00000000 IDBL0 [R/W] -------0 IFDR1 [R/W] 00000000
ITMK0 [R/W] 00----11 11111111 IFN1 [R] 00000000 IBCR1 [R/W] 00000000 IDAR0 [R/W] 00000000 IFRN1 [R/W] 00000000 IBSR1 [R/W] 00000000
I2C Interface 0
ITBA1 [R/W] ------00 00000000 ISMK1 [R/W] 01111111 ICCR1 [R/W] 0-011111 IFCR2 [R/W] 00-00000 ISBA1 [R/W] 00000000 IDBL1 [R/W] -------0 IFDR2 [R/W] 00000000
ITMK1 [R/W] 00----11 11111111 IFN2 [R] 00000000 IBCR2 [R/W] 00000000 IDAR1 [R/W] 00000000 IFRN2 [R/W] 00000000 IBSR2 [R/W] 00000000
I2C Interface 1
ITBA2 [R/W] ------00 00000000 ISMK2 [R/W] 01111111 ICCR2 [R/W] 0-011111 ISBA2 [R/W] 00000000 IDBL2 [R/W] -------0
ITMK2 [R/W] 00----11 11111111 IDAR2 [R/W] 00000000
I2C Interface 2
(Continued)
27
MB91319R Series
Address 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000114H to 00011FH 000120H 000124H 000128H 00012CH 000130H 000134H
Register +0 IFN3 [R] 00000000 IBCR3 [R/W] 00000000 +1 IFRN3 [R/W] 00000000 IBSR3 [R/W] 00000000 +2 IFCR3 [R/W] 00-00000 +3 IFDR3 [R/W] 00000000
Block
ITBA3 [R/W] ------00 00000000 ISMK3 [R/W] 01111111 ICCR3 [R/W] 0-011111 T0TCR [R/W] 00000000 ISBA3 [R/W] 00000000 IDBL3 [R/W] -------0 T0R [R/W] ---00000
ITMK3 [R/W] 00----11 11111111 T0LPCR [R/W] -----000 IDAR3 [R/W] 00000000 T0CCR [R/W] 0-010000
I2C Interface 3
T0DRR [R/W] XXXXXXXX XXXXXXXX T1LPCR [R/W] -----000 T1CCR [R/W] 0-000000
T0CRR [R/W] XXXXXXXX XXXXXXXX T1TCR[R/W] 00000000 T1R [R/W] ---00000
T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000
T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000 Multi function Timer
T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000
T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000
T3DRR [R/W] XXXXXXXX XXXXXXXX TMODE [R/W] -------- -----0- PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX
T3CRR [R/W] XXXXXXXX XXXXXXXX PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 00000000 PCNL0 [R/W] 00000000 Reserved
PPG0
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1 [R/W] 00000000 PCNL1 [R/W] 00000000
PPG1
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 00000000 PCNL2 [R/W] 00000000
PPG2
(Continued) 28
MB91319R Series
Address 000138H 00013CH 000140H to 00014CH 000150H to 00015CH 000160H 000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H 000188H 00018CH 000190H 000194H 000198H 00019CH
Register +0 +1 +2 +3 PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX PCSR3[W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 00000000 PCNL3 [R/W] 00000000
Block
PPG3
Reserved
DSLC00 0------CSYSEP0 -101-011 HCNT0 00000000 CSTB0 11111111 ID1C0 0-----00 IDSTB0 11111111 DSAC10 ---000-0 DSLC01 0------CSYTSEP1 -101-011 HCNT1 00000000 CSTB1 11111111 ID1C1 0-----00 IDSTB1 11111111 DSAC11 ---000-0 DSLC10 -011---HMASK0 --100000 C21H0 0-111111 CDTH0 11111111 ID20H0 0-111111 IDDAT00 --000000 DSAC20 10110011 DSLC11 -011---HMASK1 --100000 C21H1 0-111111 CDTH1 11111111 ID20H1 0-111111 IDDAT01 --000000 DSAC21 10110011 CCDC0 00-00011 HCLR0 ---00110 CRIP0 11111111 CDAT00 00000000 IDREF0 0-111111 IDDAT10 00000000 DSAC30 00-00-00 CCDC1 00-00011 HCLR1 ---00110 CRIP1 11111111 CDAT01 00000000 IDREF1 0-111111 IDDAT11 00000000 DSAC31 00-00-00 VSEP0 00--0001 FLD0 00100000 CRIC0 000-0000 CDAT10 00000000 IDTH0 11111111 IDDAT20 --000000 VSEP1 00--0001 FLD1 00100000 CRIC1 000-0000 CDAT1 00000000 IDTH1 11111111 IDDAT21 --000000
Reserved
CC decoder 0 channel
CC decoder 1 channel
(Continued) 29
MB91319R Series
Address 0001A0H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 0002FCH 000300H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH
Register +0 +1 DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX +2 +3
Block
Reserved
DMAC
DMAC
Reserved DMAC
Reserved BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued)
Bit Search Module
30
MB91319R Series
Address 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH
Register +0 DDR0 [R/W] 00000000 DDR4 [R/W] 00000000 DDR8 [R/W] 00000000 DDRC [R/W] 00000000 PFR0 [R/W] 0--00000 PFR4 [R/W] 0000--00 PFR8 [R/W] 11111111 PFRC [R/W] 1111---1 +1 DDR1 [R/W] 00000000 DDR5 [R/W] 00000000 DDR9 [R/W] 00000000 PFR1 [R/W] 00000000 PFR5 [R/W] 11111111 PFR9 [R/W] 11111111 PFRD [R/W] ---11111 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 ICR02[R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111 +2 DDR2 [R/W] 00000000 DDRA [R/W] -----000 PFR2 [R/W] 00000000 PFR6 [R/W] 11111111 PFRA [R/W] 11111111 +3 DDR3 [R/W] 00000000 DDR7 [R/W] --000000 DDRB [R/W] 00000000 PFR3 [R/W] 00000000 PFR7 [R/W] 11111111 PFRB [R/W] 11111111
Block
R-bus Port Direction Register
R-bus Port Function Register
Reserved
Interrupt Control Unit
(Continued) 31
MB91319R Series
Address 000470H to 00047CH 000480H 000484H 000488H 00048CH 000490H 000494H to 0005FCH 000600H to 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H
Register +0 +1 RSRR [R/W] 10000000*2 CLKR [R/W] 00000000*1 WPCR [R/W] B 00---000 OSCR [R/W] B 00---000 STCR [R/W] 00110011*2 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00*1 DIVR0 [R/W] 00000011*1 OSCCR [R/W] XXXXXXX0 CTBR [W] XXXXXXXX DIVR1[R/W] 00000000*1 +2 +3
Block
Reserved
Clock Control Unit
Reserved Watch Timer Main Oscillation Stabilization Wait Timer Reserved
Reserved
ESTS0 [R/W] X0000000 ECTL0 [R/W] 0X000000 ECNT0 [W] XXXXXXXX ESTS1 [R/W] XXXXXXXX ECTL1 [R/W] 00000000 ECNT1 [W] XXXXXXXX ESTS2 [R] 1XXXXXXX ECTL2 [W] 000X0000 EUSA [W] XXX00000 EDTR1 [W] XXXXXXXX XXXXXXXX EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ECTL3 [R/W] 00X00X11 EDTC [W] 0000XXXX
Reserved
EWP1 [R] 00000000 00000000 EDTR0 [W] XXXXXXXX XXXXXXXX
DSU
(Continued)
32
MB91319R Series
Address 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH
Register +0 +1 +2 +3 EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
DSU
Reserved (Continued)
33
MB91319R Series
(Continued) Address 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH 007000H 007004H 007008H to 0070FFH 007100H 007104H FNCR [R/W] 0110X000 FNWT [R/W] 00010011 FLCR [R/W] 0110X000 FLWC [R/W] 00010011 Font Flash I/F Register +0 +1 +2 +3 DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reserved Block
DMAC
Program Flash I/F
Reserved
*1 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset. *2 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset by the INIT pin.
34
MB91319R Series
Address 050000H to 050024H 050028H to 05FFFFH 060000H 060004H 060008H 06000CH to 06001FH 060020H 060024H 060028H 06002CH 060030H 060034H 060038H 06003CH 060040H 060044H 060048H to 06005FH 060060H 060064H
Register +0 +1 Reserved +2 +3
Block
Reserved
Reserved FIFO0o [R] XXXXXXXX XXXXXXXX FIFO1 [R] XXXXXXXX XXXXXXXX FIFO3 [R] XXXXXXXX XXXXXXXX Reserved CONT1 [R/W] 000XX0XX XXX00000 CONT3 [R/W] XXXXXXXX XXX00000 CONT5 [R/W] XXXXXXXX XXXX00XX CONT7 [R/W] XXXXXXXX XXX00000 CONT9 [R/W] 0XX0XXXX 0XXX0000 TTSIZE [R/W] 00010001 00010001 Reserved Reserved RSIZE0 [R] XXXXXXXX XXXX0000 RSIZE1 [R] XXXXXXXX X0000000 Reserved ST1 [R/W] XXXXXX00 00000000 Reserved Reserved Reserved FIFO0i [W] XXXXXXXX XXXXXXXX FIFO2 [W] XXXXXXXX XXXXXXXX
Reserved
Reserved CONT2 [R/W] XXXXXXXX XXX00000 CONT4 [R/W] XXXXXXXX XXX00000 CONT6 [R/W] XXXXXXXX XXXX00XX CONT8 [R/W] XXXXXXXX XXX00000 CONT10 [R/W] 00000000 X00000XX TRSIZE [R/W] 00010001 00010001
USB Function
Reserved
(Continued)
35
MB91319R Series
Address 060068H 06006CH 060070H to 06007FH 060080H to 06FFFFH 078000H 078004H 078008H 07800CH 078010H 078014H 078018H 07801CH 078020H 078024H 078028H 07802CH 078030H 078034H 078038H 07803CH
Register +0 +1 +2 +3 ST2 [R] XXXXXXXX X0000000 ST4 [R/W] XXXXX000 00000000 Reserved ST3 [R/W] 00XXXXXX X0000000 ST5 [R/W] 0XX00XXX XX000000
Block
USB Function
Reserved OSD_VADR [W] XXXXXXXX XXXXXXXX OSD_CD2 [W] XXXXXXXX XXXXXXXX OSD_RCD2 [W] XXXXXXXX XXXXXXXX OSD_SOC2 [W] XXXXXXXX XXXXXXXX OSD_HDPC [W] XXXXXXXX XXXXXXXX OSD_SBFCC [W] XXXXXXXX XXXXXXXX OSD_GFCC [W] XXXXXXXX XXXXXXXX OSD_SBCC2 [W] XXXXXXXX XXXXXXXX OSD_SPCC2 [W] XXXXXXXX XXXXXXXX OSD_SPCC4 [W] XXXXXXXX XXXXXXXX OSD_IOC2 [W] XXXXXXXX XXXXXXXX OSD_DPC2 [W] XXXXXXXX XXXXXXXX OSD_DPC4 [W] XXXXXXXX XXXXXXXX OSD_PLT0 [W] XXXXXXXX XXXXXXXX OSD_CD1 [W] XXXXXXXX XXXXXXXX OSD_RCD1 [W] XXXXXXXX XXXXXXXX OSD_SOC1 [W] XXXXXXXX 0000XXXX OSD_VDPC [W] XXXXXXXX XXXXXXXX OSD_CVSC [W] XXXXXXXX XXXXXXXX OSD_THCC [W] XXXXXXXX XXXXXXXX OSD_SBCC1 [W] XXXXXXXX XXXXXXXX OSD_SPCC1 [W] XXXXXXXX XXXXXXXX OSD_SPCC3 [W] XXXXXXXX XXXXXXXX OSD_SYNCC [W] XXXXXXXX XXXXXXXX OSD_IOC1 [W] XXXXXXXX XXXXXX00 OSD_DPC1 [W] XXXXXXXX XXXXXXXX OSD_DPC3 [W] XXXXXXXX XXXXXXXX OSD_IRC [W] XXXXXXXX XXXXXXXX OSD_PLT1 [W] XXXXXXXX XXXXXXXX
Reserved
OSDC (MAIN)
(Continued) 36
MB91319R Series
Address 078040H 078044H 078048H 07804CH 078050H 078054H 078058H 07805CH 078060H 078064H 078068H 07806CH 078070H 078074H 078078H 07807CH to 0780FFH 078100H 078104H 078108H 07810CH
Register +0 +1 +2 +3 OSD_PLT2 [W] XXXXXXXX XXXXXXXX OSD_PLT4 [W] XXXXXXXX XXXXXXXX OSD_PLT6 [W] XXXXXXXX XXXXXXXX OSD_PLT8 [W] XXXXXXXX XXXXXXXX OSD_PLT10 [W] XXXXXXXX XXXXXXXX OSD_PLT12 [W] XXXXXXXX XXXXXXXX OSD_PLT14 [W] XXXXXXXX XXXXXXXX OSD_ACT1 [W] XXXXXXXX XXXXXXXX OSD_PLACC11 [W] XXXXXXXX XXXXXXXX OSD_PLACC2 [W] XXXXXXXX XXXXXXXX OSD_PLBCC11 [W] XXXXXXXX XXXXXXXX OSD_PLBCC2 [W] XXXXXXXX XXXXXXXX OSD_PLCC11[W] XXXXXXXX XXXXXXXX OSD_PLCC2[W] XXXXXXXX XXXXXXXX OSD_CSC1 [W] XXXXXXXX XXXXXXXX CCOSD_VADR [W] XXXXXXXX XXXXXXXX CCOSD_CD2 [W] XXXXXXXX XXXXXXXX CCOSD_RCD2 [W] XXXXXXXX XXXXXXXX CCOSD_SOC2 [W] XXXXXXXX XXXXXXXX OSD_PLT3 [W] XXXXXXXX XXXXXXXX OSD_PLT5 [W] XXXXXXXX XXXXXXXX OSD_PLT7 [W] XXXXXXXX XXXXXXXX OSD_PLT9 [W] XXXXXXXX XXXXXXXX OSD_PLT11 [W] XXXXXXXX XXXXXXXX OSD_PLT13 [W] XXXXXXXX XXXXXXXX OSD_PLT15 [W] XXXXXXXX XXXXXXXX OSD_ACT2 [W] XXXXXXXX XXXXXXXX OSD_PLACC12 [W] XXXXXXXX XXXXXXXX OSD_PLACC3 [W] XXXXXXXX XXXXXXXX OSD_PLBCC12 [W] XXXXXXXX XXXXXXXX OSD_PLBCC3 [W] XXXXXXXX XXXXXXXX OSD_PLCC12[W] XXXXXXXX XXXXXXXX OSD_PLCC3[W] XXXXXXXX XXXXXXXX OSD_CSC2 [W] XXXXXXXX XXXXXXXX CCOSD_CD1 [W] XXXXXXXX XXXXXXXX CCOSD_RCD1 [W] XXXXXXXX XXXXXXXX CCOSD_SOC1 [W] XXXXXXXX 0000XXXX CCOSD_VDPC [W] XXXXXXXX XXXXXXXX
Block
OSDC (MAIN)
Reserved
OSDC (CC)
(Continued) 37
MB91319R Series
(Continued) Address 078110H 078114H 078118H 07811CH 078120H 078124H 078128H 07812CH 078130H 078134H 078138H 07813CH 078140H 078144H 078148H 07814CH 078150H 078154H 078158H 07815CH 078160H to 07FFFFH Register +0 +1 +2 +3 CCOSD_HDPC [W] XXXXXXXX XXXXXXXX CCOSD_DPC2 [W] XXXXXXXX XXXXXXXX CCOSD_DPC4 [W] XXXXXXXX XXXXXXXX CCOSD_PLT0 [W] XXXXXXXX XXXXXXXX CCOSD_PLT2 [W] XXXXXXXX XXXXXXXX CCOSD_PLT4 [W] XXXXXXXX XXXXXXXX CCOSD_PLT6 [W] XXXXXXXX XXXXXXXX CCOSD_PLT8 [W] XXXXXXXX XXXXXXXX CCOSD_PLT10 [W] XXXXXXXX XXXXXXXX CCOSD_PLT12 [W] XXXXXXXX XXXXXXXX CCOSD_PLT14 [W] XXXXXXXX XXXXXXXX Reserved CCOSD_CVSC [W] XXXXXXXX XXXXXXXX CCOSD_THCC [W] XXXXXXXX XXXXXXXX CCOSD_DPC1 [W] XXXXXXXX XXXXXXXX CCOSD_DPC3 [W] XXXXXXXX XXXXXXXX CCOSD_IRC [W] XXXXXXXX XXXXXXXX CCOSD_PLT1 [W] XXXXXXXX XXXXXXXX CCOSD_PLT3 [W] XXXXXXXX XXXXXXXX CCOSD_PLT5 [W] XXXXXXXX XXXXXXXX CCOSD_PLT7 [W] XXXXXXXX XXXXXXXX CCOSD_PLT9 [W] XXXXXXXX XXXXXXXX CCOSD_PLT11 [W] XXXXXXXX XXXXXXXX CCOSD_PLT13 [W] XXXXXXXX XXXXXXXX CCOSD_PLT15 [W] XXXXXXXX XXXXXXXX Reserved OSDC (CC) Block
38
MB91319R Series
INTERRUPT FACTORS, INTERRUPT VECTORS, AND INTERRUPT REGISTER
Interrupt number Interrupt factor Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction System reserved System reserved Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 (USB function) External interrupt 5 (OSDC-MAIN) External interrupt 6 (OSDC-CC) System reserved Reload timer 0 Reload timer 1 Reload timer 2 UART0 (Reception completed) UART1 (Reception completed) UART2 (Reception completed) UART0 (Transmission completed) UART1 (Transmission completed)
Decimal Hexadecimal
Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H
Address of TBR default 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H
RN 8 9 10 0 1 2 3 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
(Continued)
39
MB91319R Series
Interrupt number Interrupt factor UART2 (Transmission completed) DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D converter PPG0 PPG1 PPG2 PPG3 PWC CCD0 CCD1 Main oscillation wait Time-base timer overflow System reserved Watch timer I2C ch.0 I C ch.1 I C ch.2 I2C ch.3 UART3 (Reception completed) UART4 (Reception completed) UART3 (Transmission completed) UART4 (Transmission completed) Multi-functional timer 0 Multi-functional timer 1 Multi-functional timer 2 Multi-functional timer 3 System reserved Delay interrupt factor bit System reserved (Used by REALOS) System reserved (Used by REALOS)
2 2
Decimal
Hexadecimal
Interrupt level ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H
Address of TBR default 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H
RN 5
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41
(Continued) 40
MB91319R Series
(Continued) Interrupt number Interrupt factor System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction
Decimal Hexadecimal
Interrupt level
Offset 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H
Address of TBR default 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
RN
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF

41
MB91319R Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage * Analog power supply voltage * Input voltage * Analog pin input voltage * Output voltage * Storage temperature Symbol VDDE (3.3 V) VDDI (1.8 V) AVCC VI VIA VO Tstg Rating Min VSS - 0.5 VSS - 0.3 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 - 40 Max VSS + 4.0 VSS + 2.5 VSS + 4.0 VDDE + 0.5 AVcc + 0.5 VCC + 0.5 + 125 Unit V V V V V V C
* : The parameter is based on VSS =AVSS =0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(VSS = AVSS =0 V) Parameter Operating temperature Power supply voltage Analog power supply voltage Symbol Ta VDDE (3.3 V) VDDI (1.8 V) AVCC Value Min - 10 3.00 1.65 3.00 Max + 70 3.6 1.95 VDDE Unit C V V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
42
MB91319R Series
3. DC Characteristics
(1) CPU * MB91FV319R, MB91F318R/F318S (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol ICCT Conditions Watch mode Ta = + 25 C, fclk = 32 kHz Normal operation Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Main sleep mode Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Sub RUN mode Ta = + 25 C, fclk = 32 kHz Main stop mode Ta = + 25 C, fclk = 0 kHz Ta = + 70 C, fclk = 0 kHz "H" level input voltage VIH Value Min VCC x 0.8 Typ 400 700 140 140 80 80 500 900 240 50 1900 300 Max 900 1000 180 190 100 110 1200 1300 800 100 8800 500 VCC mA Dot clock PLL stop A A A V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, DCKI, VSYNC, HSYNC1 to HSYNC3 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH (Continued) Dot clock PLL stop USB clock stop mA Unit A Remarks Dot clock PLL stop USB clock stop Dot clock at 90 MHz MB91F318R/F318S only
ICC Current dissipation (upper : 1.8V lower : 3.3V)
ICCS
ICCL
ICCH
"L" level input voltage
VIL
VCC = 3.3 V
VSS
VCC x 0.2
V
"H" level output voltage
VOH
VCC = 3.3 V, IOH = - 4 mA
VCC - 0.5
VCC
V
43
MB91319R Series
(Continued) Parameter Symbol Conditions Value Min Typ Max Unit Remarks P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH
"L" level output voltage
VOL
VCC = 3.3 V, IOL = 4 mA
VSS
0.4
V
Input leak current I2C bus switch connection resistor Analog RGB reference voltage Analog RGB reference resistor Analog RGB output impedance
IIL
-5
+5
A Between SCL2 and SCL3 Between SDA2 and SDA3 Between SCL3 and SCL4 Between SDA3 and SDA4 VREF
RBS
130
VREF
1.05
1.10
1.15
V
RREF
2.4
2.7
k
Between VR0 and VSSR
RL
150
160
ROUT, GOUT, BOUT
44
MB91319R Series
* MB91316/A Symbol ICCT
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Conditions Watch mode Ta = + 25 C, fclk = 32 kHz Normal operation Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Main sleep mode Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Sub RUN mode Ta = + 25 C, fclk = 32 kHz Main stop mode Ta = + 25 C, fclk = 0 kHz Ta = + 70 C, fclk = 0 kHz Value Min VCC x 0.8 Typ 300 700 110 110 70 70 400 900 150 50 1200 300 Max 600 1000 130 140 90 100 800 1300 500 100 5500 500 VCC mA Dot clock PLL stop A A A V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, DCKI, VSYNC, HSYNC1 to HSYNC3 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH (Continued) Dot clock PLL stop USB clock stop mA Dot clock at 90 MHz Unit A Remarks Dot clock PLL stop USB clock stop
Parameter
ICC Current dissipation (upper : 1.8V lower : 3.3V)
ICCS
ICCL
ICCH
"H" level input voltage
VIH
"L" level input voltage
VIL
VCC = 3.3 V
VSS
VCC x 0.2
V
"H" level output voltage
VOH
VCC = 3.3 V, IOH = - 4 mA
VCC - 0.5
VCC
V
45
MB91319R Series
(Continued) Parameter Symbol Conditions Value Min Typ Max Unit Remarks P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P74, P80 to P87, P90 to P97, PA0 to PA2, PB0 to PB4, PC0 to PC7, B0 to B2, G0 to G2, R0 to R2, VOB1, VOB2, DCKO, FH
"L" level output voltage
VOL
VCC = 3.3 V, IOL = 4 mA
VSS
0.4
V
Input leak current I2C bus switch connection resistor Analog RGB reference voltage Analog RGB reference resistor Analog RGB output impedance
IIL
-5
+5
A Between SCL2 and SCL3 Between SDA2 and SDA3 Between SCL3 and SCL4 Between SDA3 and SDA4 VREF
RBS
130
VREF
1.05
1.10
1.15
V
RREF
2.4
2.7
k
Between VR0 and VSSR
RL
150
160
ROUT, GOUT, BOUT
46
MB91319R Series
(2) USB * DC Characteristics (1) (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter "H" level output voltage "L" level output voltage "H" level output current
Symbol
Pin
Conditions IOH = - 100 A IOL = 100 A At Full Speed Mode VOH = VDDE - 0.4 V At Low Speed Mode VOH = VDDE - 0.4 V At Full Speed Mode VOL = 0.4 V At Low Speed Mode VOL = 0.4 V
Value Min VDDE - 0.2 0 - 20 -6 20 6 Typ Max VDDE 0.2 300 5
Unit Remarks V V mA mA mA mA mA *1 A *2
VOH VOL
IOH
"L" level output current Output shortcircuit current Input leak current
IOL
IOS ILZ

*1 : About the output short-circuit current IOS Output short-circuit current IOS is the maximum current that flows when the output pin is connected to VDDE or VSS (within the maximum rating) . Monitor the short-circuit current "H" level "H" output
Short-circuited at GND level 3-State Enable "L" Short-circuited at VDDE level "L" level
"L" output
Monitor the short-circuit current 3-State Enable "L"
About the output short-circuit current : The current is "the short-circuit current per differential output pin". As the USB I/O buffer is a differential output, the short-circuit current should be considered for both of the output pins. (Continued)
47
MB91319R Series
(Continued) *2 : About measurement of "Z" leakage current ILZ Input leakage current ILZ is measured with the USB I/O buffer in the high-impedance state when the VDDE or VSS voltage is applied to the bidirectional pin. Monitor the leakage current "Z" output 0 V and VDD level applied to output pin
3-State Enable "H"
48
MB91319R Series
* DC Characteristics (2) Conform to the USB Specification Revision 2.0 Full speed. (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Input Voltage : High (driven) Low Differential Input Sensitivity Common Mode Input Voltage Output Voltage : Low High (driven) Differential Output Signal Voltage Terminations : Pull-Up Resistor on Upstream Port Pull-Down Resistor on Downstream Port Termination voltage for upstream port pull-up RPU RPD VTERM 1.425 1.425 3.0 1.575 1.575 3.6 k k V 1.5 k 5% 1.5 k 5% *5 VOL VOH VCRS 0.0 2.8 1.3 0.3 3.6 2.0 V V V *3 *3 *4 VIH VIL VDI VCM 2.0 0.2 0.8 0.8 2.5 V V V V *1 *1 *2 *2 Symbol Value Min Max Unit Remarks
*1 : About input voltage VIH, VIL The switching threshold voltage of the USB I/O buffer's single-end receiver is set within the range from VIL (Max) = 0.8 V to VIH (Min) = 2.0 V (TTL input standard) . For VIH and VIL, the LSI has some hysteresis to reduce noise susceptibility. *2 : About input voltage VDI, VCM A differential receiver is used to receive USB differential data signals. The differential receiver has a differential input sensitivity of 200 mV when the differential data input falls within the range from 0.8 V to 2.5 V with respect to the local ground reference level. The above voltage range is referred to as common-mode input voltage range.
1.0
Minimum operating input sensitivity (V)
0.2
0.8
2.5
Common mode input voltage (V) (Continued)
49
MB91319R Series
(Continued) *3 : About output voltage VOL, VOH The output driving performance levels of the driver are 0.3 V or less (to 3.6 V, 1.5 k load) in the low state (VOL) and 2.8 V or more (to ground, 1.5 k load) in the high state (VOH) . *4 : About output voltage VCRS The cross voltage of the external differential output signals (D+ and D-) for the USB I/O buffer falls within the range from 1.3 V to 2.0 V.
D+ Max 2.0 (V)
VCRS standard range
Max 1.3 (V) D-
*5 : About terminations VTERM VTERM indicates the pull-up voltage at the upstream port.
50
MB91319R Series
4. AC Characteristics
(1) Clock Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin Conditions Value Min Max Unit Remarks
Clock frequency
fC
X0, X1
9.0
10.2
PLL system (operation at a maximum MHz internal speed of 40 MHz by quadrupling a self-oscillation frequency of 10 MHz via PLL) MHz CPU system (tCP = 1/fCP) MHz Peripheral system (tCPP = 1/fCPP) MHz External bus system (tCPT = 1/fCPT)
fCP Internal operating clock frequency fCPP fCPT
2.25* 2.25* 2.25*
40.8 20.4 20.4
* : The numeric value when inputting the 9 MHz (the minimum clock frequency) to X0 and using the PLL system and the gear ratio 1/16 of the oscillation circuit. (2) Reset Input (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter INIT input time (at power-on) INIT input time (other than at power-on) INIT input time (at returning from stop) Note: tCP is the internal clock time. Refer to "(1) Clock Timing". tINTL INIT Symbol Pin
Conditions
Value Min 20 + tCP x 10 20 + Max
Unit s ns s
tINTL
INIT
0.2 VCC
51
MB91319R Series
(3) UART Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Serial clock cycle time SCK SO delay time Valid SIN SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO delay time Valid SI SCK Valid SCK valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK4 SCK0 to SCK4, SO0 to SO4 SCK0 to SCK4, SI0 to SI4 SCK0 to SCK4, SI0 to SI4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4, SO0 to SO4 SCK0 to SCK4, SI0 to SI4 SCK0 to SCK4, SI0 to SI4 External shift lock mode Internal shift lock mode Conditions Value Min 8 tCPP - 80 100 60 4 tCPP 4 tCPP 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns
Notes : * tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing". * The above specifications are for the CLK synchronous mode. * Internal shift clock mode
tSCYC
SCK0 to SCK4
VOH VOL tSLOV VOL
SO0 to SO4
VOH VOL tIVSH tSHIX VOH VOL
SI0 to SI4
VOH VOL
* External shift clock mode
tSLSH tSHSL VOH VOH tSLOV VOH VOH
SCK0 to SCK4
SO0 to SO4
VOH VOL tIVSH tSHIX VOH VOL
SI0 to SI4
VOH VOL
52
MB91319R Series
(4) Reload timer clock , PPG timer input, multi-functional timer input timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin TIN0 to TIN2, PPG0 to PPG3, TRG0 to TRG3, TMI0 to TMI3 Conditions Value Min Max Unit
Input pulse width
tTIWH tTIWL
2 tCPP
ns
Note : tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing".
tTIWH
tTIWL
(5) Trigger Input Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter A/D activation trigger input time Symbol tATGX Pin ATRG Conditions Value Min 5 tCPP Max Unit ns
Note : tCPP indicates the peripheral clock cycle time. Refer to "(1) Clock Timing".
tATGX
ATRG
53
MB91319R Series
(6) USB interface (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Symbol Pin X0B, X1B Input clock frequency tUCYC X0B At Full Speed Mode At Full Speed Mode At Full Speed Mode Conditions Value Min Typ Max Unit Remarks Self-oscillation 500 ppm accuracy *1 tUCYC = 1 / fUCYC External input 500 ppm accuracy *1 tUCYC = 1 / fUCYC *2
48*1 MHz
Rise Time
tUTFR
UDP/ UDM UDP/ UDM UDP/ UDM UDP, UDM
4
20
ns
Fall Time
tUTFF
4
20
ns
*2
Differential Rise and Fall Timing Matching Driver Output Resistor

90

111.11
%
*2
28
44
*3
tUCYC
X0B (X1B)
UDP
10%
90%
90% 10%
UDM
tUTFR
tUTFF
*1 : The AC characteristics of the USB interface conform to USB Specification Revision 2.0 Full speed. *2 : About driver characteristics tUTFR, tUTFF, tUTFRFM These items specify the differential data signal rise (Rise Time) and fall (Fall time) times. These are defined as the times between 10% to 90% of the output signal voltage. For the full-speed buffer, tUTFR and tUTFF are specified such that the tUTFR/tUTFF ratio falls within 10% to minimize RFI radiation. (Continued) 54
MB91319R Series
(Continued) *3 : About driver characteristics ZDRV USB full-speed connection is performed via a shielded twisted-pair cable at a characteristic impedance of 90 15%. The USB Standard stipulates that the USB driver's output impedance must be within the range of 28 to 44 . The USB Standard also stipulates that a discrete serial resistor (Rs) must be added to have balance while satisfying the above standard. The output impedance of the USB I/O buffer on this LSI is about 3 to 19 . Therefore, serial resistor RS to be added must be 25 to 30 (27 recommended) .
Rs TxD+ 28 to 44 Equiv. Imped
Rs TxD- 28 to 44 Equiv. Imped
3-State
Driver output impedance 3 to 19 Rs serial resistor: 25 to 30 Add a serial resistor of preferably 27
55
MB91319R Series
(7) Analog RGB (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Analog RGB output delay Analog RGB output settling time Symbol Pin ROUT, GOUT, BOUT ROUT, GOUT, BOUT Conditions Value Min Typ 12 Max Unit Remarks
tVAD
tVAS
VREF = 1.1 V, VDDR = VDDG = VDDB = 2.5 V, VRO* = 2.7 k
ns
50 MHz (Max)
20
ns
* : VRO is an external resistor for DAC. * Display signal output timing
DCKI
tVAD
1 LSB
ROUT GOUT BOUT
tVAS
1 LSB
56
MB91319R Series
(8) Digital RGB Vertical synchronous, horizontal synchronous, and display output control signal input timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Horizontal sync signal cycle time Horizontal sync signal pulse width Horizontal sync signal setup time Horizontal sync signal hold time Vertical sync signal setup time Vertical sync signal hold time Input sync signal rise/fall time Symbol tHCYC tWH tDHST tDHHD tHVST tHVHD tDR tDF Pin Value Min 20 4 0 5 3 Max 6 1H* - 5
2
Unit Dot clock Dot clock s ns ns Dot clock H*2 ns
Remarks
HSYNC1 to HSYNC3 100 + tWH HSYNC1 to HSYNC3 HSYNC1 to HSYNC3 VSYNC HSYNC1 to HSYNC3, VSYNC
*1
2
*1 : During the horizontal sync signal pulse period, the device stops its internal OSDC operation, disabling writing to the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle to ensure that : horizontal sync signal pulse width < VRAM write cycle. Precisely, adjust the command issuance interval not to issue command 2 or command 4 (VRAM write command) more than twice in the horizontal sync signal pulse width period. If the above condition is not satisfied, the device may fail writing to VRAM. *2 : 1H is assumed to be one horizontal sync signal period. * Horizontal sync signal, display output control signal input timing
DCKI
0.8 VDD 0.2 VDD tDHST tDHHD
0.8 VDD
0.8 VDD 0.2 VDD
HSYNC1 to HSYNC3
0.2 VDD
tDR, tDF
57
MB91319R Series
* Horizontal sync signal input
tHCYC tDF tWH tDR 0.8 VDD 0.2 VDD
HSYNC1 to HSYNC3
0.8 VDD
0.8 VDD 0.2 VDD
* Vertical sync signal input timing * VSYNC detection at the leading edge of HSYNC
tDF tWH tDR 0.8 VDD 0.2 VDD tHVHD
HSYNC1 to HSYNC3
0.8 VDD 0.2 VDD tHVST
tDF 0.8 VDD
tDR 0.8 VDD
VSYNC
0.2 VDD 0.2 VDD
* VSYNC detection at the trailing edge of HSYNC
tDF tWH tDR 0.8 VDD 0.2 VDD tHVST tHVHD
HSYNC1 to HSYNC3
0.8 VDD 0.2 VDD
tDF 0.8 VDD
tDR 0.8 VDD
VSYNC
0.2 VDD
0.2 VDD
58
MB91319R Series
(9) Display signal timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Dot clock cycle time Dot clock pulse time Dot clock output delay time 1 Symbol tDIF tDIWH tDIWL tPDCS Pin DCKI DCKI DCKO R0 to R2, B0 to B2, G0 to G2, VOB1, VOB2 R0 to R2, B0 to B2, G0 to G2, VOB1, VOB2 Value Min 11 5 5 3 Max 90 8 Unit MHz ns ns ns Remarks *1 *1 *2
Display signal output delay time I1
tPDI1
2
8
ns
*2
Display signal output delay time O1
tPDO1
-4
+5
ns
*2
*1 : Input a continuous dot clock signal without a break. *2 : Output load 16 pF Note : The actual display output varies depending on how the display output/position is controlled for each display layer. * Display signal output timing
tDIF tDIWH 0.8 VDD 0.2 VDD tPDCS tPDCS tDIWL 0.8 VDD 0.2 VDD
DCKI
0.8 VDD
DCKO
tPDO1 tPDI1
0.2 VDD
R0 to R2 B0 to B2 G0 to G2 VOB1, VOB2
0.8 VDD 0.2 VDD
59
MB91319R Series
(10-a) External circuit for data slicer (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Video signal input level Symbol VVIN Pin VIN0, VIN1 Value Min 1.0 Typ Max 1.5 Unit Vp-p
(10-b) External circuit for data slicer (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter Coupling capacitor for VIN pin Clamping resistor Input resistor for VIN pin Low-pass filter capacitor for VIN Power supply bypass capacitor Resistor for video signal input buffer Video signal input level correcting resistor Video signal input level correcting resistor Symbol Pin VIN0, VIN1 VIN0, VIN1 VIN0, VIN1 VDDIS, VSSS Value Min Typ 10 Max 0.1 Unit Remarks Ceramic capacitor with B rating or higher, 10% tolerance 5% tolerance 5% tolerance Ceramic capacitor with B rating or higher, 10% tolerance Ceramic capacitor 5% tolerance 5% tolerance 5% tolerance
CVIN
F M pF F k k k
RCL RIN
1 0
C1
82
CBP R1 R2 R3
0.1 2.2 4.7 12
60
MB91319R Series
External recommended circuit for data slicer (1) When the input composite video signals have been DC clamped
2.5 V VDDIS CBP 5V VSSS R1 RIN VIN0, VIN1 RCL CVIN
2SB709A equivalent
R3 C1
R2
Composite video signal (2 Vp-p)
(2) When the input composite video signals have not been DC clamped
2.5 V VDDIS CBP 5V VSSS R1 RIN VIN0, VIN1 RCL CVIN R2 R3 C1 10 k
Add this resistor
(5% tolerance)
2SB709A equivalent
Composite video signal (2 Vp-p)
61
MB91319R Series
(11) I2C timing * At master mode operating (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock Bus free time between [STOP condition] and [START condition] SCL SDA output delay time Setup time of [repeat START condition] SCL SDA Hold time of [repeat START condition] SDA SCL Setup time of [STOP condition] SCL SDA SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) Symbol fSCL tLOW tHIGH tBUS Conditions Typical mode Min 0 4.7 4.0 4.7 4.7 Max 100 5 x M*1 High-speed mode*3 Min 0 1.3 0.6 1.3 0.6 Max 400 5 x M*1 Unit kHz s s s ns s After that, the first clock pulse is generated. Remarks
tDLDAT
tSUSTA
R = 1 k C = 50 pF*4
tHDSTA
4.0
0.6
s
tSUSTO
4.0 2 x M*1 250

0.6 2 x M*1 100*2

s s ns
tHDDAT tSUDAT
*1 : M = Resource clock cycle (ns) *2 : A Fast-mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When the device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
62
MB91319R Series
* At slave mode operating (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V) Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock SCL SDA output delay time Bus free time between [STOP condition and START condition] SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) Setup time of [repeat START condition] SCL SDA Hold time of [repeat START condition] SDA SCL Setup time of [STOP condition] SCL SDA Symbol fSCL tLOW tHIGH tDLDAT Conditions Typical mode Min 0 4.7 4.0 4.7 2 x M*1 250 Max 100 5 x M*1 High-speed mode*3 Min 0 1.3 0.6 1.3 2 x M*1 100*2 Max 400 5 x M*1 Unit kHz s s ns s s ns s After that, the first clock pulse is generated. Remarks
tBUS
tHDDAT tSUDAT
R = 1 k C = 50 pF*4
tSUSTA
4.7
0.6
tHDSTA
4.0
0.6
s
tSUSTO
4.0
0.6
s
*1 : M = Resource clock cycle (ns) *2 : A Fast-mode I2C bus device can be used for a standard mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When the device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
63
MB91319R Series
5. Power-on Sequence
* The power supplies must be turned on in the VDDI AVCC, AVRH, VDDE order and off in the VDDE AVCC, AVRH, VDDI order. * Turn on VDDE before applying on the analog power supply AVCC and the analog signal.
6. Electrical Characteristics for the A/D Converter
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V, VSS = 0 V, VSSE = VSSI = AVSS = 0 V, AVRH = 3.0 V to 3.6 V) Parameter Resolution Total error*1 Nonlinear error*1 Differential linear error* Full transition voltage*1 Conversion time Power supply voltage (analog + digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Interchannel disparity *1 : Measured in the CPU sleep state *2 : Depends on the clock cycle of the clock signal supplied to peripheral resources.
1
Value Min - 5.5 - 3.5 - 2.0 - 4.0 AVRH - 5.5 8.5*2 Typ Max 10 + 5.5 + 3.5 + 2.0 + 6.0 AVRH + 3.0 3.3 100 27 4
Unit bit LSB LSB LSB LSB LSB s mA A pF LSB
Remarks
Zero transition voltage*1
AVCC = 3.3 V, AVRH = 3.3 V (at CPU sleep)
64
MB91319R Series
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
* Analog input circuit
R
Analog input During sampling : ON
C
Comparator
MB91316/316A/F318R MB91F318S/FV319R
Note : The values are reference values.
R 5 k (Max)
C 27 pF (Max)
* The relationship between the external impedance and minimum sampling time [External impedance = 0 k to 100 k]
MB91316/316A/F318R/F318S/FV319A
100 20
[External impedance = 0 k to 20 k]
MB91316/316A/F318R/F318S/FV319A
External impedance (k)
External impedance (k)
90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
Minimum sampling time (s)
Minimum sampling time (s)
* About errors * As |AVRH - AVSS| becomes smaller, values of relative errors grow larger. 65
MB91319R Series
Definition of A/D Converter Terms * Resolution Indicates the ability of the A/D converter to discriminate analog variation * Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device's zero transition point (00 0000 000000 0000 0001) and full scale transition point (11 1111 1110 11 1111 1111) * Differential linear error Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output code. [Linear Error]
3FFH 3FEH 3FDH {1 LSB x (N - 1) + VTO}
Actual variation Theoretical
[Differential linear error]
N - 1H VFST (measured value)
Actual variation
Digital output
004H 003H 002H
VNT (measured value)
Actual variation Theoretical values
Digital output
N - 2H
N - 1H
V(N - 1)T (measured value) VNT (measured value)
001H
N - 2H
Actual variation
VTO (measured value) AVRH AVRL AVRH
AVRL
Analog input Linear error in digital output N = VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N + 1) T - VNT 1 LSB -1
Analog input
[LSB] [LSB]
Differential linear error in digital output N = 1 LSB = 1 LSB" = N VFST - VOT 1022 [V] [V]
AVRH - AVRL 1024
(theoretical value)
: A/D converter digital output value
VOT : Voltage at which the digital output transitions from "000"H to "001"H. VFST : Voltage at which the digital output transitions from "3FE"H to "3FF"H. VNT : Voltage at which the digital output transitions from (N-1) to N. 66
MB91319R Series
* Total error Expresses the difference between actual and theoretical values as error, including zero transition error, fullscale error, and linearity error.
[Total error]
3FFH
Actual variation
3FEH {1 LSB x (N - 1) + 0.5 LSB 3FDH
1.5 LSB
Digital output
004H 003H 002H
theoretical value
VNT (measured value)
Actual variation
001H 0.5 LSB AVRL AVRH
Analog input
Total error in digital output N =
VNT - {1 LSB" x (N - 1) + 0.5 LSB"} [LSB] 1 LSB"
N : A/D converter digital output value VOT" (theoretical value) = AVRL + 0.5 LSB" [V] VFST" (theoretical value) = AVRH - 1.5 LSB" [V] VNT : Voltage at which digital output transitions from (N-1) to N.
67
MB91319R Series
FLASH MEMORY PROGRAM/ERASE CHARACTERISTICS
(VCC = 3.3 V, Ta = + 25 C) Parameter Sector erase time Byte programming time Chip programming time Erase/program cycle Value Min 10000 Typ 0.5 6 3.4 Max 2.0 100 56 Unit s s s cycle Remarks Excludes 00H programming prior erasure. Excludes system-level overhead. Excludes system-level overhead.
68
MB91319R Series
ORDERING INFORMATION
Part number MB91FV319RPMC-ESE1 MB91F318RPMC-G-XXXE1 MB91F318RPMC-GXXX-XXXXE1 MB91F318SPMC-G-XXXE1 MB91F318SPMC-GXXX-XXXXE1 MB91316PMC-G-XXXE1 MB91316APMC-G-XXXE1 Package 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) 176-pin plastic LQFP (FPT-176P-M07) Remarks For development tool With CC decoder. Without Fujitsu Flash programming. With CC decoder. With Fujitsu Flash programming. Without CC decoder. Without Fujitsu Flash programming. Without CC decoder. With Fujitsu Flash programming. Without CC decoder. With CC decoder.
69
MB91319R Series
PACKAGE DIMENSION
176-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.50 mm 24.0 x 24.0 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP (FPT-176P-M07)
26.000.20(1.024.008)SQ *24.000.10(.945.004)SQ
Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
132
89
133
88
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0~8
0.100.10 (.004.004) (Stand off)
INDEX 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010)
176
45
"A" LEAD No.
1 44
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
70
MB91319R Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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